/* SPDX-License-Identifier: GPL-2.0+ */
// $Module: reg_G1_PINMUX_REG $
// $RegisterBank Version: v1.0.00 $
// $Author:  $
// $Date: Tue, 28 Feb 2023 09:47:20 AM $
//

//GEN REG ADDR/OFFSET/MASK
#define  G1_PINMUX_REG_REG_RGMII0_TXD0  0x0
#define  G1_PINMUX_REG_REG_RGMII0_TXD1  0x4
#define  G1_PINMUX_REG_REG_RGMII0_TXD2  0x8
#define  G1_PINMUX_REG_REG_RGMII0_TXD3  0xc
#define  G1_PINMUX_REG_REG_RGMII0_TXCTRL  0x10
#define  G1_PINMUX_REG_REG_RGMII0_RXD0  0x14
#define  G1_PINMUX_REG_REG_RGMII0_RXD1  0x18
#define  G1_PINMUX_REG_REG_RGMII0_RXD2  0x1c
#define  G1_PINMUX_REG_REG_RGMII0_RXD3  0x20
#define  G1_PINMUX_REG_REG_RGMII0_RXCTRL  0x24
#define  G1_PINMUX_REG_REG_RGMII0_TXC  0x28
#define  G1_PINMUX_REG_REG_RGMII0_RXC  0x2c
#define  G1_PINMUX_REG_REG_RGMII0_REFCLKO  0x30
#define  G1_PINMUX_REG_REG_RGMII0_IRQ  0x34
#define  G1_PINMUX_REG_REG_RGMII0_MDC  0x38
#define  G1_PINMUX_REG_REG_RGMII0_MDIO  0x3c
#define  G1_PINMUX_REG_REG_RGMII1_TXD0  0x40
#define  G1_PINMUX_REG_REG_RGMII1_TXD1  0x44
#define  G1_PINMUX_REG_REG_RGMII1_TXD2  0x48
#define  G1_PINMUX_REG_REG_RGMII1_TXD3  0x4c
#define  G1_PINMUX_REG_REG_RGMII1_TXCTRL  0x50
#define  G1_PINMUX_REG_REG_RGMII1_RXD0  0x54
#define  G1_PINMUX_REG_REG_RGMII1_RXD1  0x58
#define  G1_PINMUX_REG_REG_RGMII1_RXD2  0x5c
#define  G1_PINMUX_REG_REG_RGMII1_RXD3  0x60
#define  G1_PINMUX_REG_REG_RGMII1_RXCTRL  0x64
#define  G1_PINMUX_REG_REG_RGMII1_TXC  0x68
#define  G1_PINMUX_REG_REG_RGMII1_RXC  0x6c
#define  G1_PINMUX_REG_REG_RGMII1_REFCLKO  0x70
#define  G1_PINMUX_REG_REG_RGMII1_IRQ  0x74
#define  G1_PINMUX_REG_REG_RGMII1_MDC  0x78
#define  G1_PINMUX_REG_REG_RGMII1_MDIO  0x7c
#define  G1_PINMUX_REG_REG_RGMII0_TXD0_PU_EN   0x0
#define  G1_PINMUX_REG_REG_RGMII0_TXD0_PU_EN_OFFSET 2
#define  G1_PINMUX_REG_REG_RGMII0_TXD0_PU_EN_MASK   0x4
#define  G1_PINMUX_REG_REG_RGMII0_TXD0_PU_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_TXD0_PD_EN   0x0
#define  G1_PINMUX_REG_REG_RGMII0_TXD0_PD_EN_OFFSET 3
#define  G1_PINMUX_REG_REG_RGMII0_TXD0_PD_EN_MASK   0x8
#define  G1_PINMUX_REG_REG_RGMII0_TXD0_PD_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_TXD0_PIN_SEL_EN   0x0
#define  G1_PINMUX_REG_REG_RGMII0_TXD0_PIN_SEL_EN_OFFSET 4
#define  G1_PINMUX_REG_REG_RGMII0_TXD0_PIN_SEL_EN_MASK   0xf0
#define  G1_PINMUX_REG_REG_RGMII0_TXD0_PIN_SEL_EN_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII0_TXD0_DRI_SEL   0x0
#define  G1_PINMUX_REG_REG_RGMII0_TXD0_DRI_SEL_OFFSET 8
#define  G1_PINMUX_REG_REG_RGMII0_TXD0_DRI_SEL_MASK   0xf00
#define  G1_PINMUX_REG_REG_RGMII0_TXD0_DRI_SEL_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII0_TXD0_SCT_EN   0x0
#define  G1_PINMUX_REG_REG_RGMII0_TXD0_SCT_EN_OFFSET 12
#define  G1_PINMUX_REG_REG_RGMII0_TXD0_SCT_EN_MASK   0x1000
#define  G1_PINMUX_REG_REG_RGMII0_TXD0_SCT_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_TXD0_OEX_EN   0x0
#define  G1_PINMUX_REG_REG_RGMII0_TXD0_OEX_EN_OFFSET 13
#define  G1_PINMUX_REG_REG_RGMII0_TXD0_OEX_EN_MASK   0x2000
#define  G1_PINMUX_REG_REG_RGMII0_TXD0_OEX_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_TXD1_PU_EN   0x4
#define  G1_PINMUX_REG_REG_RGMII0_TXD1_PU_EN_OFFSET 2
#define  G1_PINMUX_REG_REG_RGMII0_TXD1_PU_EN_MASK   0x4
#define  G1_PINMUX_REG_REG_RGMII0_TXD1_PU_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_TXD1_PD_EN   0x4
#define  G1_PINMUX_REG_REG_RGMII0_TXD1_PD_EN_OFFSET 3
#define  G1_PINMUX_REG_REG_RGMII0_TXD1_PD_EN_MASK   0x8
#define  G1_PINMUX_REG_REG_RGMII0_TXD1_PD_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_TXD1_PIN_SEL_EN   0x4
#define  G1_PINMUX_REG_REG_RGMII0_TXD1_PIN_SEL_EN_OFFSET 4
#define  G1_PINMUX_REG_REG_RGMII0_TXD1_PIN_SEL_EN_MASK   0xf0
#define  G1_PINMUX_REG_REG_RGMII0_TXD1_PIN_SEL_EN_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII0_TXD1_DRI_SEL   0x4
#define  G1_PINMUX_REG_REG_RGMII0_TXD1_DRI_SEL_OFFSET 8
#define  G1_PINMUX_REG_REG_RGMII0_TXD1_DRI_SEL_MASK   0xf00
#define  G1_PINMUX_REG_REG_RGMII0_TXD1_DRI_SEL_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII0_TXD1_SCT_EN   0x4
#define  G1_PINMUX_REG_REG_RGMII0_TXD1_SCT_EN_OFFSET 12
#define  G1_PINMUX_REG_REG_RGMII0_TXD1_SCT_EN_MASK   0x1000
#define  G1_PINMUX_REG_REG_RGMII0_TXD1_SCT_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_TXD1_OEX_EN   0x4
#define  G1_PINMUX_REG_REG_RGMII0_TXD1_OEX_EN_OFFSET 13
#define  G1_PINMUX_REG_REG_RGMII0_TXD1_OEX_EN_MASK   0x2000
#define  G1_PINMUX_REG_REG_RGMII0_TXD1_OEX_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_TXD2_PU_EN   0x8
#define  G1_PINMUX_REG_REG_RGMII0_TXD2_PU_EN_OFFSET 2
#define  G1_PINMUX_REG_REG_RGMII0_TXD2_PU_EN_MASK   0x4
#define  G1_PINMUX_REG_REG_RGMII0_TXD2_PU_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_TXD2_PD_EN   0x8
#define  G1_PINMUX_REG_REG_RGMII0_TXD2_PD_EN_OFFSET 3
#define  G1_PINMUX_REG_REG_RGMII0_TXD2_PD_EN_MASK   0x8
#define  G1_PINMUX_REG_REG_RGMII0_TXD2_PD_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_TXD2_PIN_SEL_EN   0x8
#define  G1_PINMUX_REG_REG_RGMII0_TXD2_PIN_SEL_EN_OFFSET 4
#define  G1_PINMUX_REG_REG_RGMII0_TXD2_PIN_SEL_EN_MASK   0xf0
#define  G1_PINMUX_REG_REG_RGMII0_TXD2_PIN_SEL_EN_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII0_TXD2_DRI_SEL   0x8
#define  G1_PINMUX_REG_REG_RGMII0_TXD2_DRI_SEL_OFFSET 8
#define  G1_PINMUX_REG_REG_RGMII0_TXD2_DRI_SEL_MASK   0xf00
#define  G1_PINMUX_REG_REG_RGMII0_TXD2_DRI_SEL_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII0_TXD2_SCT_EN   0x8
#define  G1_PINMUX_REG_REG_RGMII0_TXD2_SCT_EN_OFFSET 12
#define  G1_PINMUX_REG_REG_RGMII0_TXD2_SCT_EN_MASK   0x1000
#define  G1_PINMUX_REG_REG_RGMII0_TXD2_SCT_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_TXD2_OEX_EN   0x8
#define  G1_PINMUX_REG_REG_RGMII0_TXD2_OEX_EN_OFFSET 13
#define  G1_PINMUX_REG_REG_RGMII0_TXD2_OEX_EN_MASK   0x2000
#define  G1_PINMUX_REG_REG_RGMII0_TXD2_OEX_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_TXD3_PU_EN   0xc
#define  G1_PINMUX_REG_REG_RGMII0_TXD3_PU_EN_OFFSET 2
#define  G1_PINMUX_REG_REG_RGMII0_TXD3_PU_EN_MASK   0x4
#define  G1_PINMUX_REG_REG_RGMII0_TXD3_PU_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_TXD3_PD_EN   0xc
#define  G1_PINMUX_REG_REG_RGMII0_TXD3_PD_EN_OFFSET 3
#define  G1_PINMUX_REG_REG_RGMII0_TXD3_PD_EN_MASK   0x8
#define  G1_PINMUX_REG_REG_RGMII0_TXD3_PD_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_TXD3_PIN_SEL_EN   0xc
#define  G1_PINMUX_REG_REG_RGMII0_TXD3_PIN_SEL_EN_OFFSET 4
#define  G1_PINMUX_REG_REG_RGMII0_TXD3_PIN_SEL_EN_MASK   0xf0
#define  G1_PINMUX_REG_REG_RGMII0_TXD3_PIN_SEL_EN_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII0_TXD3_DRI_SEL   0xc
#define  G1_PINMUX_REG_REG_RGMII0_TXD3_DRI_SEL_OFFSET 8
#define  G1_PINMUX_REG_REG_RGMII0_TXD3_DRI_SEL_MASK   0xf00
#define  G1_PINMUX_REG_REG_RGMII0_TXD3_DRI_SEL_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII0_TXD3_SCT_EN   0xc
#define  G1_PINMUX_REG_REG_RGMII0_TXD3_SCT_EN_OFFSET 12
#define  G1_PINMUX_REG_REG_RGMII0_TXD3_SCT_EN_MASK   0x1000
#define  G1_PINMUX_REG_REG_RGMII0_TXD3_SCT_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_TXD3_OEX_EN   0xc
#define  G1_PINMUX_REG_REG_RGMII0_TXD3_OEX_EN_OFFSET 13
#define  G1_PINMUX_REG_REG_RGMII0_TXD3_OEX_EN_MASK   0x2000
#define  G1_PINMUX_REG_REG_RGMII0_TXD3_OEX_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_TXCTRL_PU_EN   0x10
#define  G1_PINMUX_REG_REG_RGMII0_TXCTRL_PU_EN_OFFSET 2
#define  G1_PINMUX_REG_REG_RGMII0_TXCTRL_PU_EN_MASK   0x4
#define  G1_PINMUX_REG_REG_RGMII0_TXCTRL_PU_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_TXCTRL_PD_EN   0x10
#define  G1_PINMUX_REG_REG_RGMII0_TXCTRL_PD_EN_OFFSET 3
#define  G1_PINMUX_REG_REG_RGMII0_TXCTRL_PD_EN_MASK   0x8
#define  G1_PINMUX_REG_REG_RGMII0_TXCTRL_PD_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_TXCTRL_PIN_SEL_EN   0x10
#define  G1_PINMUX_REG_REG_RGMII0_TXCTRL_PIN_SEL_EN_OFFSET 4
#define  G1_PINMUX_REG_REG_RGMII0_TXCTRL_PIN_SEL_EN_MASK   0xf0
#define  G1_PINMUX_REG_REG_RGMII0_TXCTRL_PIN_SEL_EN_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII0_TXCTRL_DRI_SEL   0x10
#define  G1_PINMUX_REG_REG_RGMII0_TXCTRL_DRI_SEL_OFFSET 8
#define  G1_PINMUX_REG_REG_RGMII0_TXCTRL_DRI_SEL_MASK   0xf00
#define  G1_PINMUX_REG_REG_RGMII0_TXCTRL_DRI_SEL_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII0_TXCTRL_SCT_EN   0x10
#define  G1_PINMUX_REG_REG_RGMII0_TXCTRL_SCT_EN_OFFSET 12
#define  G1_PINMUX_REG_REG_RGMII0_TXCTRL_SCT_EN_MASK   0x1000
#define  G1_PINMUX_REG_REG_RGMII0_TXCTRL_SCT_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_TXCTRL_OEX_EN   0x10
#define  G1_PINMUX_REG_REG_RGMII0_TXCTRL_OEX_EN_OFFSET 13
#define  G1_PINMUX_REG_REG_RGMII0_TXCTRL_OEX_EN_MASK   0x2000
#define  G1_PINMUX_REG_REG_RGMII0_TXCTRL_OEX_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_RXD0_PU_EN   0x14
#define  G1_PINMUX_REG_REG_RGMII0_RXD0_PU_EN_OFFSET 2
#define  G1_PINMUX_REG_REG_RGMII0_RXD0_PU_EN_MASK   0x4
#define  G1_PINMUX_REG_REG_RGMII0_RXD0_PU_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_RXD0_PD_EN   0x14
#define  G1_PINMUX_REG_REG_RGMII0_RXD0_PD_EN_OFFSET 3
#define  G1_PINMUX_REG_REG_RGMII0_RXD0_PD_EN_MASK   0x8
#define  G1_PINMUX_REG_REG_RGMII0_RXD0_PD_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_RXD0_PIN_SEL_EN   0x14
#define  G1_PINMUX_REG_REG_RGMII0_RXD0_PIN_SEL_EN_OFFSET 4
#define  G1_PINMUX_REG_REG_RGMII0_RXD0_PIN_SEL_EN_MASK   0xf0
#define  G1_PINMUX_REG_REG_RGMII0_RXD0_PIN_SEL_EN_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII0_RXD0_DRI_SEL   0x14
#define  G1_PINMUX_REG_REG_RGMII0_RXD0_DRI_SEL_OFFSET 8
#define  G1_PINMUX_REG_REG_RGMII0_RXD0_DRI_SEL_MASK   0xf00
#define  G1_PINMUX_REG_REG_RGMII0_RXD0_DRI_SEL_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII0_RXD0_SCT_EN   0x14
#define  G1_PINMUX_REG_REG_RGMII0_RXD0_SCT_EN_OFFSET 12
#define  G1_PINMUX_REG_REG_RGMII0_RXD0_SCT_EN_MASK   0x1000
#define  G1_PINMUX_REG_REG_RGMII0_RXD0_SCT_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_RXD0_OEX_EN   0x14
#define  G1_PINMUX_REG_REG_RGMII0_RXD0_OEX_EN_OFFSET 13
#define  G1_PINMUX_REG_REG_RGMII0_RXD0_OEX_EN_MASK   0x2000
#define  G1_PINMUX_REG_REG_RGMII0_RXD0_OEX_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_RXD1_PU_EN   0x18
#define  G1_PINMUX_REG_REG_RGMII0_RXD1_PU_EN_OFFSET 2
#define  G1_PINMUX_REG_REG_RGMII0_RXD1_PU_EN_MASK   0x4
#define  G1_PINMUX_REG_REG_RGMII0_RXD1_PU_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_RXD1_PD_EN   0x18
#define  G1_PINMUX_REG_REG_RGMII0_RXD1_PD_EN_OFFSET 3
#define  G1_PINMUX_REG_REG_RGMII0_RXD1_PD_EN_MASK   0x8
#define  G1_PINMUX_REG_REG_RGMII0_RXD1_PD_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_RXD1_PIN_SEL_EN   0x18
#define  G1_PINMUX_REG_REG_RGMII0_RXD1_PIN_SEL_EN_OFFSET 4
#define  G1_PINMUX_REG_REG_RGMII0_RXD1_PIN_SEL_EN_MASK   0xf0
#define  G1_PINMUX_REG_REG_RGMII0_RXD1_PIN_SEL_EN_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII0_RXD1_DRI_SEL   0x18
#define  G1_PINMUX_REG_REG_RGMII0_RXD1_DRI_SEL_OFFSET 8
#define  G1_PINMUX_REG_REG_RGMII0_RXD1_DRI_SEL_MASK   0xf00
#define  G1_PINMUX_REG_REG_RGMII0_RXD1_DRI_SEL_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII0_RXD1_SCT_EN   0x18
#define  G1_PINMUX_REG_REG_RGMII0_RXD1_SCT_EN_OFFSET 12
#define  G1_PINMUX_REG_REG_RGMII0_RXD1_SCT_EN_MASK   0x1000
#define  G1_PINMUX_REG_REG_RGMII0_RXD1_SCT_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_RXD1_OEX_EN   0x18
#define  G1_PINMUX_REG_REG_RGMII0_RXD1_OEX_EN_OFFSET 13
#define  G1_PINMUX_REG_REG_RGMII0_RXD1_OEX_EN_MASK   0x2000
#define  G1_PINMUX_REG_REG_RGMII0_RXD1_OEX_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_RXD2_PU_EN   0x1c
#define  G1_PINMUX_REG_REG_RGMII0_RXD2_PU_EN_OFFSET 2
#define  G1_PINMUX_REG_REG_RGMII0_RXD2_PU_EN_MASK   0x4
#define  G1_PINMUX_REG_REG_RGMII0_RXD2_PU_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_RXD2_PD_EN   0x1c
#define  G1_PINMUX_REG_REG_RGMII0_RXD2_PD_EN_OFFSET 3
#define  G1_PINMUX_REG_REG_RGMII0_RXD2_PD_EN_MASK   0x8
#define  G1_PINMUX_REG_REG_RGMII0_RXD2_PD_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_RXD2_PIN_SEL_EN   0x1c
#define  G1_PINMUX_REG_REG_RGMII0_RXD2_PIN_SEL_EN_OFFSET 4
#define  G1_PINMUX_REG_REG_RGMII0_RXD2_PIN_SEL_EN_MASK   0xf0
#define  G1_PINMUX_REG_REG_RGMII0_RXD2_PIN_SEL_EN_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII0_RXD2_DRI_SEL   0x1c
#define  G1_PINMUX_REG_REG_RGMII0_RXD2_DRI_SEL_OFFSET 8
#define  G1_PINMUX_REG_REG_RGMII0_RXD2_DRI_SEL_MASK   0xf00
#define  G1_PINMUX_REG_REG_RGMII0_RXD2_DRI_SEL_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII0_RXD2_SCT_EN   0x1c
#define  G1_PINMUX_REG_REG_RGMII0_RXD2_SCT_EN_OFFSET 12
#define  G1_PINMUX_REG_REG_RGMII0_RXD2_SCT_EN_MASK   0x1000
#define  G1_PINMUX_REG_REG_RGMII0_RXD2_SCT_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_RXD2_OEX_EN   0x1c
#define  G1_PINMUX_REG_REG_RGMII0_RXD2_OEX_EN_OFFSET 13
#define  G1_PINMUX_REG_REG_RGMII0_RXD2_OEX_EN_MASK   0x2000
#define  G1_PINMUX_REG_REG_RGMII0_RXD2_OEX_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_RXD3_PU_EN   0x20
#define  G1_PINMUX_REG_REG_RGMII0_RXD3_PU_EN_OFFSET 2
#define  G1_PINMUX_REG_REG_RGMII0_RXD3_PU_EN_MASK   0x4
#define  G1_PINMUX_REG_REG_RGMII0_RXD3_PU_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_RXD3_PD_EN   0x20
#define  G1_PINMUX_REG_REG_RGMII0_RXD3_PD_EN_OFFSET 3
#define  G1_PINMUX_REG_REG_RGMII0_RXD3_PD_EN_MASK   0x8
#define  G1_PINMUX_REG_REG_RGMII0_RXD3_PD_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_RXD3_PIN_SEL_EN   0x20
#define  G1_PINMUX_REG_REG_RGMII0_RXD3_PIN_SEL_EN_OFFSET 4
#define  G1_PINMUX_REG_REG_RGMII0_RXD3_PIN_SEL_EN_MASK   0xf0
#define  G1_PINMUX_REG_REG_RGMII0_RXD3_PIN_SEL_EN_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII0_RXD3_DRI_SEL   0x20
#define  G1_PINMUX_REG_REG_RGMII0_RXD3_DRI_SEL_OFFSET 8
#define  G1_PINMUX_REG_REG_RGMII0_RXD3_DRI_SEL_MASK   0xf00
#define  G1_PINMUX_REG_REG_RGMII0_RXD3_DRI_SEL_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII0_RXD3_SCT_EN   0x20
#define  G1_PINMUX_REG_REG_RGMII0_RXD3_SCT_EN_OFFSET 12
#define  G1_PINMUX_REG_REG_RGMII0_RXD3_SCT_EN_MASK   0x1000
#define  G1_PINMUX_REG_REG_RGMII0_RXD3_SCT_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_RXD3_OEX_EN   0x20
#define  G1_PINMUX_REG_REG_RGMII0_RXD3_OEX_EN_OFFSET 13
#define  G1_PINMUX_REG_REG_RGMII0_RXD3_OEX_EN_MASK   0x2000
#define  G1_PINMUX_REG_REG_RGMII0_RXD3_OEX_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_RXCTRL_PU_EN   0x24
#define  G1_PINMUX_REG_REG_RGMII0_RXCTRL_PU_EN_OFFSET 2
#define  G1_PINMUX_REG_REG_RGMII0_RXCTRL_PU_EN_MASK   0x4
#define  G1_PINMUX_REG_REG_RGMII0_RXCTRL_PU_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_RXCTRL_PD_EN   0x24
#define  G1_PINMUX_REG_REG_RGMII0_RXCTRL_PD_EN_OFFSET 3
#define  G1_PINMUX_REG_REG_RGMII0_RXCTRL_PD_EN_MASK   0x8
#define  G1_PINMUX_REG_REG_RGMII0_RXCTRL_PD_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_RXCTRL_PIN_SEL_EN   0x24
#define  G1_PINMUX_REG_REG_RGMII0_RXCTRL_PIN_SEL_EN_OFFSET 4
#define  G1_PINMUX_REG_REG_RGMII0_RXCTRL_PIN_SEL_EN_MASK   0xf0
#define  G1_PINMUX_REG_REG_RGMII0_RXCTRL_PIN_SEL_EN_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII0_RXCTRL_DRI_SEL   0x24
#define  G1_PINMUX_REG_REG_RGMII0_RXCTRL_DRI_SEL_OFFSET 8
#define  G1_PINMUX_REG_REG_RGMII0_RXCTRL_DRI_SEL_MASK   0xf00
#define  G1_PINMUX_REG_REG_RGMII0_RXCTRL_DRI_SEL_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII0_RXCTRL_SCT_EN   0x24
#define  G1_PINMUX_REG_REG_RGMII0_RXCTRL_SCT_EN_OFFSET 12
#define  G1_PINMUX_REG_REG_RGMII0_RXCTRL_SCT_EN_MASK   0x1000
#define  G1_PINMUX_REG_REG_RGMII0_RXCTRL_SCT_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_RXCTRL_OEX_EN   0x24
#define  G1_PINMUX_REG_REG_RGMII0_RXCTRL_OEX_EN_OFFSET 13
#define  G1_PINMUX_REG_REG_RGMII0_RXCTRL_OEX_EN_MASK   0x2000
#define  G1_PINMUX_REG_REG_RGMII0_RXCTRL_OEX_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_TXC_PU_EN   0x28
#define  G1_PINMUX_REG_REG_RGMII0_TXC_PU_EN_OFFSET 2
#define  G1_PINMUX_REG_REG_RGMII0_TXC_PU_EN_MASK   0x4
#define  G1_PINMUX_REG_REG_RGMII0_TXC_PU_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_TXC_PD_EN   0x28
#define  G1_PINMUX_REG_REG_RGMII0_TXC_PD_EN_OFFSET 3
#define  G1_PINMUX_REG_REG_RGMII0_TXC_PD_EN_MASK   0x8
#define  G1_PINMUX_REG_REG_RGMII0_TXC_PD_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_TXC_PIN_SEL_EN   0x28
#define  G1_PINMUX_REG_REG_RGMII0_TXC_PIN_SEL_EN_OFFSET 4
#define  G1_PINMUX_REG_REG_RGMII0_TXC_PIN_SEL_EN_MASK   0xf0
#define  G1_PINMUX_REG_REG_RGMII0_TXC_PIN_SEL_EN_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII0_TXC_DRI_SEL   0x28
#define  G1_PINMUX_REG_REG_RGMII0_TXC_DRI_SEL_OFFSET 8
#define  G1_PINMUX_REG_REG_RGMII0_TXC_DRI_SEL_MASK   0xf00
#define  G1_PINMUX_REG_REG_RGMII0_TXC_DRI_SEL_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII0_TXC_SCT_EN   0x28
#define  G1_PINMUX_REG_REG_RGMII0_TXC_SCT_EN_OFFSET 12
#define  G1_PINMUX_REG_REG_RGMII0_TXC_SCT_EN_MASK   0x1000
#define  G1_PINMUX_REG_REG_RGMII0_TXC_SCT_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_TXC_OEX_EN   0x28
#define  G1_PINMUX_REG_REG_RGMII0_TXC_OEX_EN_OFFSET 13
#define  G1_PINMUX_REG_REG_RGMII0_TXC_OEX_EN_MASK   0x2000
#define  G1_PINMUX_REG_REG_RGMII0_TXC_OEX_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_RXC_PU_EN   0x2c
#define  G1_PINMUX_REG_REG_RGMII0_RXC_PU_EN_OFFSET 2
#define  G1_PINMUX_REG_REG_RGMII0_RXC_PU_EN_MASK   0x4
#define  G1_PINMUX_REG_REG_RGMII0_RXC_PU_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_RXC_PD_EN   0x2c
#define  G1_PINMUX_REG_REG_RGMII0_RXC_PD_EN_OFFSET 3
#define  G1_PINMUX_REG_REG_RGMII0_RXC_PD_EN_MASK   0x8
#define  G1_PINMUX_REG_REG_RGMII0_RXC_PD_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_RXC_PIN_SEL_EN   0x2c
#define  G1_PINMUX_REG_REG_RGMII0_RXC_PIN_SEL_EN_OFFSET 4
#define  G1_PINMUX_REG_REG_RGMII0_RXC_PIN_SEL_EN_MASK   0xf0
#define  G1_PINMUX_REG_REG_RGMII0_RXC_PIN_SEL_EN_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII0_RXC_DRI_SEL   0x2c
#define  G1_PINMUX_REG_REG_RGMII0_RXC_DRI_SEL_OFFSET 8
#define  G1_PINMUX_REG_REG_RGMII0_RXC_DRI_SEL_MASK   0xf00
#define  G1_PINMUX_REG_REG_RGMII0_RXC_DRI_SEL_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII0_RXC_SCT_EN   0x2c
#define  G1_PINMUX_REG_REG_RGMII0_RXC_SCT_EN_OFFSET 12
#define  G1_PINMUX_REG_REG_RGMII0_RXC_SCT_EN_MASK   0x1000
#define  G1_PINMUX_REG_REG_RGMII0_RXC_SCT_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_RXC_OEX_EN   0x2c
#define  G1_PINMUX_REG_REG_RGMII0_RXC_OEX_EN_OFFSET 13
#define  G1_PINMUX_REG_REG_RGMII0_RXC_OEX_EN_MASK   0x2000
#define  G1_PINMUX_REG_REG_RGMII0_RXC_OEX_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_REFCLKO_PU_EN   0x30
#define  G1_PINMUX_REG_REG_RGMII0_REFCLKO_PU_EN_OFFSET 2
#define  G1_PINMUX_REG_REG_RGMII0_REFCLKO_PU_EN_MASK   0x4
#define  G1_PINMUX_REG_REG_RGMII0_REFCLKO_PU_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_REFCLKO_PD_EN   0x30
#define  G1_PINMUX_REG_REG_RGMII0_REFCLKO_PD_EN_OFFSET 3
#define  G1_PINMUX_REG_REG_RGMII0_REFCLKO_PD_EN_MASK   0x8
#define  G1_PINMUX_REG_REG_RGMII0_REFCLKO_PD_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_REFCLKO_PIN_SEL_EN   0x30
#define  G1_PINMUX_REG_REG_RGMII0_REFCLKO_PIN_SEL_EN_OFFSET 4
#define  G1_PINMUX_REG_REG_RGMII0_REFCLKO_PIN_SEL_EN_MASK   0xf0
#define  G1_PINMUX_REG_REG_RGMII0_REFCLKO_PIN_SEL_EN_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII0_REFCLKO_DRI_SEL   0x30
#define  G1_PINMUX_REG_REG_RGMII0_REFCLKO_DRI_SEL_OFFSET 8
#define  G1_PINMUX_REG_REG_RGMII0_REFCLKO_DRI_SEL_MASK   0xf00
#define  G1_PINMUX_REG_REG_RGMII0_REFCLKO_DRI_SEL_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII0_REFCLKO_SCT_EN   0x30
#define  G1_PINMUX_REG_REG_RGMII0_REFCLKO_SCT_EN_OFFSET 12
#define  G1_PINMUX_REG_REG_RGMII0_REFCLKO_SCT_EN_MASK   0x1000
#define  G1_PINMUX_REG_REG_RGMII0_REFCLKO_SCT_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_REFCLKO_OEX_EN   0x30
#define  G1_PINMUX_REG_REG_RGMII0_REFCLKO_OEX_EN_OFFSET 13
#define  G1_PINMUX_REG_REG_RGMII0_REFCLKO_OEX_EN_MASK   0x2000
#define  G1_PINMUX_REG_REG_RGMII0_REFCLKO_OEX_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_IRQ_PU_EN   0x34
#define  G1_PINMUX_REG_REG_RGMII0_IRQ_PU_EN_OFFSET 2
#define  G1_PINMUX_REG_REG_RGMII0_IRQ_PU_EN_MASK   0x4
#define  G1_PINMUX_REG_REG_RGMII0_IRQ_PU_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_IRQ_PD_EN   0x34
#define  G1_PINMUX_REG_REG_RGMII0_IRQ_PD_EN_OFFSET 3
#define  G1_PINMUX_REG_REG_RGMII0_IRQ_PD_EN_MASK   0x8
#define  G1_PINMUX_REG_REG_RGMII0_IRQ_PD_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_IRQ_PIN_SEL_EN   0x34
#define  G1_PINMUX_REG_REG_RGMII0_IRQ_PIN_SEL_EN_OFFSET 4
#define  G1_PINMUX_REG_REG_RGMII0_IRQ_PIN_SEL_EN_MASK   0xf0
#define  G1_PINMUX_REG_REG_RGMII0_IRQ_PIN_SEL_EN_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII0_IRQ_DRI_SEL   0x34
#define  G1_PINMUX_REG_REG_RGMII0_IRQ_DRI_SEL_OFFSET 8
#define  G1_PINMUX_REG_REG_RGMII0_IRQ_DRI_SEL_MASK   0xf00
#define  G1_PINMUX_REG_REG_RGMII0_IRQ_DRI_SEL_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII0_IRQ_SCT_EN   0x34
#define  G1_PINMUX_REG_REG_RGMII0_IRQ_SCT_EN_OFFSET 12
#define  G1_PINMUX_REG_REG_RGMII0_IRQ_SCT_EN_MASK   0x1000
#define  G1_PINMUX_REG_REG_RGMII0_IRQ_SCT_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_IRQ_OEX_EN   0x34
#define  G1_PINMUX_REG_REG_RGMII0_IRQ_OEX_EN_OFFSET 13
#define  G1_PINMUX_REG_REG_RGMII0_IRQ_OEX_EN_MASK   0x2000
#define  G1_PINMUX_REG_REG_RGMII0_IRQ_OEX_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_MDC_PU_EN   0x38
#define  G1_PINMUX_REG_REG_RGMII0_MDC_PU_EN_OFFSET 2
#define  G1_PINMUX_REG_REG_RGMII0_MDC_PU_EN_MASK   0x4
#define  G1_PINMUX_REG_REG_RGMII0_MDC_PU_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_MDC_PD_EN   0x38
#define  G1_PINMUX_REG_REG_RGMII0_MDC_PD_EN_OFFSET 3
#define  G1_PINMUX_REG_REG_RGMII0_MDC_PD_EN_MASK   0x8
#define  G1_PINMUX_REG_REG_RGMII0_MDC_PD_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_MDC_PIN_SEL_EN   0x38
#define  G1_PINMUX_REG_REG_RGMII0_MDC_PIN_SEL_EN_OFFSET 4
#define  G1_PINMUX_REG_REG_RGMII0_MDC_PIN_SEL_EN_MASK   0xf0
#define  G1_PINMUX_REG_REG_RGMII0_MDC_PIN_SEL_EN_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII0_MDC_DRI_SEL   0x38
#define  G1_PINMUX_REG_REG_RGMII0_MDC_DRI_SEL_OFFSET 8
#define  G1_PINMUX_REG_REG_RGMII0_MDC_DRI_SEL_MASK   0xf00
#define  G1_PINMUX_REG_REG_RGMII0_MDC_DRI_SEL_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII0_MDC_SCT_EN   0x38
#define  G1_PINMUX_REG_REG_RGMII0_MDC_SCT_EN_OFFSET 12
#define  G1_PINMUX_REG_REG_RGMII0_MDC_SCT_EN_MASK   0x1000
#define  G1_PINMUX_REG_REG_RGMII0_MDC_SCT_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_MDC_OEX_EN   0x38
#define  G1_PINMUX_REG_REG_RGMII0_MDC_OEX_EN_OFFSET 13
#define  G1_PINMUX_REG_REG_RGMII0_MDC_OEX_EN_MASK   0x2000
#define  G1_PINMUX_REG_REG_RGMII0_MDC_OEX_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_MDIO_PU_EN   0x3c
#define  G1_PINMUX_REG_REG_RGMII0_MDIO_PU_EN_OFFSET 2
#define  G1_PINMUX_REG_REG_RGMII0_MDIO_PU_EN_MASK   0x4
#define  G1_PINMUX_REG_REG_RGMII0_MDIO_PU_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_MDIO_PD_EN   0x3c
#define  G1_PINMUX_REG_REG_RGMII0_MDIO_PD_EN_OFFSET 3
#define  G1_PINMUX_REG_REG_RGMII0_MDIO_PD_EN_MASK   0x8
#define  G1_PINMUX_REG_REG_RGMII0_MDIO_PD_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_MDIO_PIN_SEL_EN   0x3c
#define  G1_PINMUX_REG_REG_RGMII0_MDIO_PIN_SEL_EN_OFFSET 4
#define  G1_PINMUX_REG_REG_RGMII0_MDIO_PIN_SEL_EN_MASK   0xf0
#define  G1_PINMUX_REG_REG_RGMII0_MDIO_PIN_SEL_EN_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII0_MDIO_DRI_SEL   0x3c
#define  G1_PINMUX_REG_REG_RGMII0_MDIO_DRI_SEL_OFFSET 8
#define  G1_PINMUX_REG_REG_RGMII0_MDIO_DRI_SEL_MASK   0xf00
#define  G1_PINMUX_REG_REG_RGMII0_MDIO_DRI_SEL_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII0_MDIO_SCT_EN   0x3c
#define  G1_PINMUX_REG_REG_RGMII0_MDIO_SCT_EN_OFFSET 12
#define  G1_PINMUX_REG_REG_RGMII0_MDIO_SCT_EN_MASK   0x1000
#define  G1_PINMUX_REG_REG_RGMII0_MDIO_SCT_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII0_MDIO_OEX_EN   0x3c
#define  G1_PINMUX_REG_REG_RGMII0_MDIO_OEX_EN_OFFSET 13
#define  G1_PINMUX_REG_REG_RGMII0_MDIO_OEX_EN_MASK   0x2000
#define  G1_PINMUX_REG_REG_RGMII0_MDIO_OEX_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_TXD0_PU_EN   0x40
#define  G1_PINMUX_REG_REG_RGMII1_TXD0_PU_EN_OFFSET 2
#define  G1_PINMUX_REG_REG_RGMII1_TXD0_PU_EN_MASK   0x4
#define  G1_PINMUX_REG_REG_RGMII1_TXD0_PU_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_TXD0_PD_EN   0x40
#define  G1_PINMUX_REG_REG_RGMII1_TXD0_PD_EN_OFFSET 3
#define  G1_PINMUX_REG_REG_RGMII1_TXD0_PD_EN_MASK   0x8
#define  G1_PINMUX_REG_REG_RGMII1_TXD0_PD_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_TXD0_PIN_SEL_EN   0x40
#define  G1_PINMUX_REG_REG_RGMII1_TXD0_PIN_SEL_EN_OFFSET 4
#define  G1_PINMUX_REG_REG_RGMII1_TXD0_PIN_SEL_EN_MASK   0xf0
#define  G1_PINMUX_REG_REG_RGMII1_TXD0_PIN_SEL_EN_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII1_TXD0_DRI_SEL   0x40
#define  G1_PINMUX_REG_REG_RGMII1_TXD0_DRI_SEL_OFFSET 8
#define  G1_PINMUX_REG_REG_RGMII1_TXD0_DRI_SEL_MASK   0xf00
#define  G1_PINMUX_REG_REG_RGMII1_TXD0_DRI_SEL_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII1_TXD0_SCT_EN   0x40
#define  G1_PINMUX_REG_REG_RGMII1_TXD0_SCT_EN_OFFSET 12
#define  G1_PINMUX_REG_REG_RGMII1_TXD0_SCT_EN_MASK   0x1000
#define  G1_PINMUX_REG_REG_RGMII1_TXD0_SCT_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_TXD0_OEX_EN   0x40
#define  G1_PINMUX_REG_REG_RGMII1_TXD0_OEX_EN_OFFSET 13
#define  G1_PINMUX_REG_REG_RGMII1_TXD0_OEX_EN_MASK   0x2000
#define  G1_PINMUX_REG_REG_RGMII1_TXD0_OEX_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_TXD1_PU_EN   0x44
#define  G1_PINMUX_REG_REG_RGMII1_TXD1_PU_EN_OFFSET 2
#define  G1_PINMUX_REG_REG_RGMII1_TXD1_PU_EN_MASK   0x4
#define  G1_PINMUX_REG_REG_RGMII1_TXD1_PU_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_TXD1_PD_EN   0x44
#define  G1_PINMUX_REG_REG_RGMII1_TXD1_PD_EN_OFFSET 3
#define  G1_PINMUX_REG_REG_RGMII1_TXD1_PD_EN_MASK   0x8
#define  G1_PINMUX_REG_REG_RGMII1_TXD1_PD_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_TXD1_PIN_SEL_EN   0x44
#define  G1_PINMUX_REG_REG_RGMII1_TXD1_PIN_SEL_EN_OFFSET 4
#define  G1_PINMUX_REG_REG_RGMII1_TXD1_PIN_SEL_EN_MASK   0xf0
#define  G1_PINMUX_REG_REG_RGMII1_TXD1_PIN_SEL_EN_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII1_TXD1_DRI_SEL   0x44
#define  G1_PINMUX_REG_REG_RGMII1_TXD1_DRI_SEL_OFFSET 8
#define  G1_PINMUX_REG_REG_RGMII1_TXD1_DRI_SEL_MASK   0xf00
#define  G1_PINMUX_REG_REG_RGMII1_TXD1_DRI_SEL_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII1_TXD1_SCT_EN   0x44
#define  G1_PINMUX_REG_REG_RGMII1_TXD1_SCT_EN_OFFSET 12
#define  G1_PINMUX_REG_REG_RGMII1_TXD1_SCT_EN_MASK   0x1000
#define  G1_PINMUX_REG_REG_RGMII1_TXD1_SCT_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_TXD1_OEX_EN   0x44
#define  G1_PINMUX_REG_REG_RGMII1_TXD1_OEX_EN_OFFSET 13
#define  G1_PINMUX_REG_REG_RGMII1_TXD1_OEX_EN_MASK   0x2000
#define  G1_PINMUX_REG_REG_RGMII1_TXD1_OEX_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_TXD2_PU_EN   0x48
#define  G1_PINMUX_REG_REG_RGMII1_TXD2_PU_EN_OFFSET 2
#define  G1_PINMUX_REG_REG_RGMII1_TXD2_PU_EN_MASK   0x4
#define  G1_PINMUX_REG_REG_RGMII1_TXD2_PU_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_TXD2_PD_EN   0x48
#define  G1_PINMUX_REG_REG_RGMII1_TXD2_PD_EN_OFFSET 3
#define  G1_PINMUX_REG_REG_RGMII1_TXD2_PD_EN_MASK   0x8
#define  G1_PINMUX_REG_REG_RGMII1_TXD2_PD_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_TXD2_PIN_SEL_EN   0x48
#define  G1_PINMUX_REG_REG_RGMII1_TXD2_PIN_SEL_EN_OFFSET 4
#define  G1_PINMUX_REG_REG_RGMII1_TXD2_PIN_SEL_EN_MASK   0xf0
#define  G1_PINMUX_REG_REG_RGMII1_TXD2_PIN_SEL_EN_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII1_TXD2_DRI_SEL   0x48
#define  G1_PINMUX_REG_REG_RGMII1_TXD2_DRI_SEL_OFFSET 8
#define  G1_PINMUX_REG_REG_RGMII1_TXD2_DRI_SEL_MASK   0xf00
#define  G1_PINMUX_REG_REG_RGMII1_TXD2_DRI_SEL_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII1_TXD2_SCT_EN   0x48
#define  G1_PINMUX_REG_REG_RGMII1_TXD2_SCT_EN_OFFSET 12
#define  G1_PINMUX_REG_REG_RGMII1_TXD2_SCT_EN_MASK   0x1000
#define  G1_PINMUX_REG_REG_RGMII1_TXD2_SCT_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_TXD2_OEX_EN   0x48
#define  G1_PINMUX_REG_REG_RGMII1_TXD2_OEX_EN_OFFSET 13
#define  G1_PINMUX_REG_REG_RGMII1_TXD2_OEX_EN_MASK   0x2000
#define  G1_PINMUX_REG_REG_RGMII1_TXD2_OEX_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_TXD3_PU_EN   0x4c
#define  G1_PINMUX_REG_REG_RGMII1_TXD3_PU_EN_OFFSET 2
#define  G1_PINMUX_REG_REG_RGMII1_TXD3_PU_EN_MASK   0x4
#define  G1_PINMUX_REG_REG_RGMII1_TXD3_PU_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_TXD3_PD_EN   0x4c
#define  G1_PINMUX_REG_REG_RGMII1_TXD3_PD_EN_OFFSET 3
#define  G1_PINMUX_REG_REG_RGMII1_TXD3_PD_EN_MASK   0x8
#define  G1_PINMUX_REG_REG_RGMII1_TXD3_PD_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_TXD3_PIN_SEL_EN   0x4c
#define  G1_PINMUX_REG_REG_RGMII1_TXD3_PIN_SEL_EN_OFFSET 4
#define  G1_PINMUX_REG_REG_RGMII1_TXD3_PIN_SEL_EN_MASK   0xf0
#define  G1_PINMUX_REG_REG_RGMII1_TXD3_PIN_SEL_EN_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII1_TXD3_DRI_SEL   0x4c
#define  G1_PINMUX_REG_REG_RGMII1_TXD3_DRI_SEL_OFFSET 8
#define  G1_PINMUX_REG_REG_RGMII1_TXD3_DRI_SEL_MASK   0xf00
#define  G1_PINMUX_REG_REG_RGMII1_TXD3_DRI_SEL_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII1_TXD3_SCT_EN   0x4c
#define  G1_PINMUX_REG_REG_RGMII1_TXD3_SCT_EN_OFFSET 12
#define  G1_PINMUX_REG_REG_RGMII1_TXD3_SCT_EN_MASK   0x1000
#define  G1_PINMUX_REG_REG_RGMII1_TXD3_SCT_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_TXD3_OEX_EN   0x4c
#define  G1_PINMUX_REG_REG_RGMII1_TXD3_OEX_EN_OFFSET 13
#define  G1_PINMUX_REG_REG_RGMII1_TXD3_OEX_EN_MASK   0x2000
#define  G1_PINMUX_REG_REG_RGMII1_TXD3_OEX_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_TXCTRL_PU_EN   0x50
#define  G1_PINMUX_REG_REG_RGMII1_TXCTRL_PU_EN_OFFSET 2
#define  G1_PINMUX_REG_REG_RGMII1_TXCTRL_PU_EN_MASK   0x4
#define  G1_PINMUX_REG_REG_RGMII1_TXCTRL_PU_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_TXCTRL_PD_EN   0x50
#define  G1_PINMUX_REG_REG_RGMII1_TXCTRL_PD_EN_OFFSET 3
#define  G1_PINMUX_REG_REG_RGMII1_TXCTRL_PD_EN_MASK   0x8
#define  G1_PINMUX_REG_REG_RGMII1_TXCTRL_PD_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_TXCTRL_PIN_SEL_EN   0x50
#define  G1_PINMUX_REG_REG_RGMII1_TXCTRL_PIN_SEL_EN_OFFSET 4
#define  G1_PINMUX_REG_REG_RGMII1_TXCTRL_PIN_SEL_EN_MASK   0xf0
#define  G1_PINMUX_REG_REG_RGMII1_TXCTRL_PIN_SEL_EN_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII1_TXCTRL_DRI_SEL   0x50
#define  G1_PINMUX_REG_REG_RGMII1_TXCTRL_DRI_SEL_OFFSET 8
#define  G1_PINMUX_REG_REG_RGMII1_TXCTRL_DRI_SEL_MASK   0xf00
#define  G1_PINMUX_REG_REG_RGMII1_TXCTRL_DRI_SEL_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII1_TXCTRL_SCT_EN   0x50
#define  G1_PINMUX_REG_REG_RGMII1_TXCTRL_SCT_EN_OFFSET 12
#define  G1_PINMUX_REG_REG_RGMII1_TXCTRL_SCT_EN_MASK   0x1000
#define  G1_PINMUX_REG_REG_RGMII1_TXCTRL_SCT_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_TXCTRL_OEX_EN   0x50
#define  G1_PINMUX_REG_REG_RGMII1_TXCTRL_OEX_EN_OFFSET 13
#define  G1_PINMUX_REG_REG_RGMII1_TXCTRL_OEX_EN_MASK   0x2000
#define  G1_PINMUX_REG_REG_RGMII1_TXCTRL_OEX_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_RXD0_PU_EN   0x54
#define  G1_PINMUX_REG_REG_RGMII1_RXD0_PU_EN_OFFSET 2
#define  G1_PINMUX_REG_REG_RGMII1_RXD0_PU_EN_MASK   0x4
#define  G1_PINMUX_REG_REG_RGMII1_RXD0_PU_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_RXD0_PD_EN   0x54
#define  G1_PINMUX_REG_REG_RGMII1_RXD0_PD_EN_OFFSET 3
#define  G1_PINMUX_REG_REG_RGMII1_RXD0_PD_EN_MASK   0x8
#define  G1_PINMUX_REG_REG_RGMII1_RXD0_PD_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_RXD0_PIN_SEL_EN   0x54
#define  G1_PINMUX_REG_REG_RGMII1_RXD0_PIN_SEL_EN_OFFSET 4
#define  G1_PINMUX_REG_REG_RGMII1_RXD0_PIN_SEL_EN_MASK   0xf0
#define  G1_PINMUX_REG_REG_RGMII1_RXD0_PIN_SEL_EN_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII1_RXD0_DRI_SEL   0x54
#define  G1_PINMUX_REG_REG_RGMII1_RXD0_DRI_SEL_OFFSET 8
#define  G1_PINMUX_REG_REG_RGMII1_RXD0_DRI_SEL_MASK   0xf00
#define  G1_PINMUX_REG_REG_RGMII1_RXD0_DRI_SEL_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII1_RXD0_SCT_EN   0x54
#define  G1_PINMUX_REG_REG_RGMII1_RXD0_SCT_EN_OFFSET 12
#define  G1_PINMUX_REG_REG_RGMII1_RXD0_SCT_EN_MASK   0x1000
#define  G1_PINMUX_REG_REG_RGMII1_RXD0_SCT_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_RXD0_OEX_EN   0x54
#define  G1_PINMUX_REG_REG_RGMII1_RXD0_OEX_EN_OFFSET 13
#define  G1_PINMUX_REG_REG_RGMII1_RXD0_OEX_EN_MASK   0x2000
#define  G1_PINMUX_REG_REG_RGMII1_RXD0_OEX_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_RXD1_PU_EN   0x58
#define  G1_PINMUX_REG_REG_RGMII1_RXD1_PU_EN_OFFSET 2
#define  G1_PINMUX_REG_REG_RGMII1_RXD1_PU_EN_MASK   0x4
#define  G1_PINMUX_REG_REG_RGMII1_RXD1_PU_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_RXD1_PD_EN   0x58
#define  G1_PINMUX_REG_REG_RGMII1_RXD1_PD_EN_OFFSET 3
#define  G1_PINMUX_REG_REG_RGMII1_RXD1_PD_EN_MASK   0x8
#define  G1_PINMUX_REG_REG_RGMII1_RXD1_PD_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_RXD1_PIN_SEL_EN   0x58
#define  G1_PINMUX_REG_REG_RGMII1_RXD1_PIN_SEL_EN_OFFSET 4
#define  G1_PINMUX_REG_REG_RGMII1_RXD1_PIN_SEL_EN_MASK   0xf0
#define  G1_PINMUX_REG_REG_RGMII1_RXD1_PIN_SEL_EN_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII1_RXD1_DRI_SEL   0x58
#define  G1_PINMUX_REG_REG_RGMII1_RXD1_DRI_SEL_OFFSET 8
#define  G1_PINMUX_REG_REG_RGMII1_RXD1_DRI_SEL_MASK   0xf00
#define  G1_PINMUX_REG_REG_RGMII1_RXD1_DRI_SEL_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII1_RXD1_SCT_EN   0x58
#define  G1_PINMUX_REG_REG_RGMII1_RXD1_SCT_EN_OFFSET 12
#define  G1_PINMUX_REG_REG_RGMII1_RXD1_SCT_EN_MASK   0x1000
#define  G1_PINMUX_REG_REG_RGMII1_RXD1_SCT_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_RXD1_OEX_EN   0x58
#define  G1_PINMUX_REG_REG_RGMII1_RXD1_OEX_EN_OFFSET 13
#define  G1_PINMUX_REG_REG_RGMII1_RXD1_OEX_EN_MASK   0x2000
#define  G1_PINMUX_REG_REG_RGMII1_RXD1_OEX_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_RXD2_PU_EN   0x5c
#define  G1_PINMUX_REG_REG_RGMII1_RXD2_PU_EN_OFFSET 2
#define  G1_PINMUX_REG_REG_RGMII1_RXD2_PU_EN_MASK   0x4
#define  G1_PINMUX_REG_REG_RGMII1_RXD2_PU_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_RXD2_PD_EN   0x5c
#define  G1_PINMUX_REG_REG_RGMII1_RXD2_PD_EN_OFFSET 3
#define  G1_PINMUX_REG_REG_RGMII1_RXD2_PD_EN_MASK   0x8
#define  G1_PINMUX_REG_REG_RGMII1_RXD2_PD_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_RXD2_PIN_SEL_EN   0x5c
#define  G1_PINMUX_REG_REG_RGMII1_RXD2_PIN_SEL_EN_OFFSET 4
#define  G1_PINMUX_REG_REG_RGMII1_RXD2_PIN_SEL_EN_MASK   0xf0
#define  G1_PINMUX_REG_REG_RGMII1_RXD2_PIN_SEL_EN_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII1_RXD2_DRI_SEL   0x5c
#define  G1_PINMUX_REG_REG_RGMII1_RXD2_DRI_SEL_OFFSET 8
#define  G1_PINMUX_REG_REG_RGMII1_RXD2_DRI_SEL_MASK   0xf00
#define  G1_PINMUX_REG_REG_RGMII1_RXD2_DRI_SEL_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII1_RXD2_SCT_EN   0x5c
#define  G1_PINMUX_REG_REG_RGMII1_RXD2_SCT_EN_OFFSET 12
#define  G1_PINMUX_REG_REG_RGMII1_RXD2_SCT_EN_MASK   0x1000
#define  G1_PINMUX_REG_REG_RGMII1_RXD2_SCT_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_RXD2_OEX_EN   0x5c
#define  G1_PINMUX_REG_REG_RGMII1_RXD2_OEX_EN_OFFSET 13
#define  G1_PINMUX_REG_REG_RGMII1_RXD2_OEX_EN_MASK   0x2000
#define  G1_PINMUX_REG_REG_RGMII1_RXD2_OEX_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_RXD3_PU_EN   0x60
#define  G1_PINMUX_REG_REG_RGMII1_RXD3_PU_EN_OFFSET 2
#define  G1_PINMUX_REG_REG_RGMII1_RXD3_PU_EN_MASK   0x4
#define  G1_PINMUX_REG_REG_RGMII1_RXD3_PU_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_RXD3_PD_EN   0x60
#define  G1_PINMUX_REG_REG_RGMII1_RXD3_PD_EN_OFFSET 3
#define  G1_PINMUX_REG_REG_RGMII1_RXD3_PD_EN_MASK   0x8
#define  G1_PINMUX_REG_REG_RGMII1_RXD3_PD_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_RXD3_PIN_SEL_EN   0x60
#define  G1_PINMUX_REG_REG_RGMII1_RXD3_PIN_SEL_EN_OFFSET 4
#define  G1_PINMUX_REG_REG_RGMII1_RXD3_PIN_SEL_EN_MASK   0xf0
#define  G1_PINMUX_REG_REG_RGMII1_RXD3_PIN_SEL_EN_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII1_RXD3_DRI_SEL   0x60
#define  G1_PINMUX_REG_REG_RGMII1_RXD3_DRI_SEL_OFFSET 8
#define  G1_PINMUX_REG_REG_RGMII1_RXD3_DRI_SEL_MASK   0xf00
#define  G1_PINMUX_REG_REG_RGMII1_RXD3_DRI_SEL_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII1_RXD3_SCT_EN   0x60
#define  G1_PINMUX_REG_REG_RGMII1_RXD3_SCT_EN_OFFSET 12
#define  G1_PINMUX_REG_REG_RGMII1_RXD3_SCT_EN_MASK   0x1000
#define  G1_PINMUX_REG_REG_RGMII1_RXD3_SCT_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_RXD3_OEX_EN   0x60
#define  G1_PINMUX_REG_REG_RGMII1_RXD3_OEX_EN_OFFSET 13
#define  G1_PINMUX_REG_REG_RGMII1_RXD3_OEX_EN_MASK   0x2000
#define  G1_PINMUX_REG_REG_RGMII1_RXD3_OEX_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_RXCTRL_PU_EN   0x64
#define  G1_PINMUX_REG_REG_RGMII1_RXCTRL_PU_EN_OFFSET 2
#define  G1_PINMUX_REG_REG_RGMII1_RXCTRL_PU_EN_MASK   0x4
#define  G1_PINMUX_REG_REG_RGMII1_RXCTRL_PU_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_RXCTRL_PD_EN   0x64
#define  G1_PINMUX_REG_REG_RGMII1_RXCTRL_PD_EN_OFFSET 3
#define  G1_PINMUX_REG_REG_RGMII1_RXCTRL_PD_EN_MASK   0x8
#define  G1_PINMUX_REG_REG_RGMII1_RXCTRL_PD_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_RXCTRL_PIN_SEL_EN   0x64
#define  G1_PINMUX_REG_REG_RGMII1_RXCTRL_PIN_SEL_EN_OFFSET 4
#define  G1_PINMUX_REG_REG_RGMII1_RXCTRL_PIN_SEL_EN_MASK   0xf0
#define  G1_PINMUX_REG_REG_RGMII1_RXCTRL_PIN_SEL_EN_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII1_RXCTRL_DRI_SEL   0x64
#define  G1_PINMUX_REG_REG_RGMII1_RXCTRL_DRI_SEL_OFFSET 8
#define  G1_PINMUX_REG_REG_RGMII1_RXCTRL_DRI_SEL_MASK   0xf00
#define  G1_PINMUX_REG_REG_RGMII1_RXCTRL_DRI_SEL_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII1_RXCTRL_SCT_EN   0x64
#define  G1_PINMUX_REG_REG_RGMII1_RXCTRL_SCT_EN_OFFSET 12
#define  G1_PINMUX_REG_REG_RGMII1_RXCTRL_SCT_EN_MASK   0x1000
#define  G1_PINMUX_REG_REG_RGMII1_RXCTRL_SCT_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_RXCTRL_OEX_EN   0x64
#define  G1_PINMUX_REG_REG_RGMII1_RXCTRL_OEX_EN_OFFSET 13
#define  G1_PINMUX_REG_REG_RGMII1_RXCTRL_OEX_EN_MASK   0x2000
#define  G1_PINMUX_REG_REG_RGMII1_RXCTRL_OEX_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_TXC_PU_EN   0x68
#define  G1_PINMUX_REG_REG_RGMII1_TXC_PU_EN_OFFSET 2
#define  G1_PINMUX_REG_REG_RGMII1_TXC_PU_EN_MASK   0x4
#define  G1_PINMUX_REG_REG_RGMII1_TXC_PU_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_TXC_PD_EN   0x68
#define  G1_PINMUX_REG_REG_RGMII1_TXC_PD_EN_OFFSET 3
#define  G1_PINMUX_REG_REG_RGMII1_TXC_PD_EN_MASK   0x8
#define  G1_PINMUX_REG_REG_RGMII1_TXC_PD_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_TXC_PIN_SEL_EN   0x68
#define  G1_PINMUX_REG_REG_RGMII1_TXC_PIN_SEL_EN_OFFSET 4
#define  G1_PINMUX_REG_REG_RGMII1_TXC_PIN_SEL_EN_MASK   0xf0
#define  G1_PINMUX_REG_REG_RGMII1_TXC_PIN_SEL_EN_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII1_TXC_DRI_SEL   0x68
#define  G1_PINMUX_REG_REG_RGMII1_TXC_DRI_SEL_OFFSET 8
#define  G1_PINMUX_REG_REG_RGMII1_TXC_DRI_SEL_MASK   0xf00
#define  G1_PINMUX_REG_REG_RGMII1_TXC_DRI_SEL_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII1_TXC_SCT_EN   0x68
#define  G1_PINMUX_REG_REG_RGMII1_TXC_SCT_EN_OFFSET 12
#define  G1_PINMUX_REG_REG_RGMII1_TXC_SCT_EN_MASK   0x1000
#define  G1_PINMUX_REG_REG_RGMII1_TXC_SCT_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_TXC_OEX_EN   0x68
#define  G1_PINMUX_REG_REG_RGMII1_TXC_OEX_EN_OFFSET 13
#define  G1_PINMUX_REG_REG_RGMII1_TXC_OEX_EN_MASK   0x2000
#define  G1_PINMUX_REG_REG_RGMII1_TXC_OEX_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_RXC_PU_EN   0x6c
#define  G1_PINMUX_REG_REG_RGMII1_RXC_PU_EN_OFFSET 2
#define  G1_PINMUX_REG_REG_RGMII1_RXC_PU_EN_MASK   0x4
#define  G1_PINMUX_REG_REG_RGMII1_RXC_PU_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_RXC_PD_EN   0x6c
#define  G1_PINMUX_REG_REG_RGMII1_RXC_PD_EN_OFFSET 3
#define  G1_PINMUX_REG_REG_RGMII1_RXC_PD_EN_MASK   0x8
#define  G1_PINMUX_REG_REG_RGMII1_RXC_PD_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_RXC_PIN_SEL_EN   0x6c
#define  G1_PINMUX_REG_REG_RGMII1_RXC_PIN_SEL_EN_OFFSET 4
#define  G1_PINMUX_REG_REG_RGMII1_RXC_PIN_SEL_EN_MASK   0xf0
#define  G1_PINMUX_REG_REG_RGMII1_RXC_PIN_SEL_EN_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII1_RXC_DRI_SEL   0x6c
#define  G1_PINMUX_REG_REG_RGMII1_RXC_DRI_SEL_OFFSET 8
#define  G1_PINMUX_REG_REG_RGMII1_RXC_DRI_SEL_MASK   0xf00
#define  G1_PINMUX_REG_REG_RGMII1_RXC_DRI_SEL_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII1_RXC_SCT_EN   0x6c
#define  G1_PINMUX_REG_REG_RGMII1_RXC_SCT_EN_OFFSET 12
#define  G1_PINMUX_REG_REG_RGMII1_RXC_SCT_EN_MASK   0x1000
#define  G1_PINMUX_REG_REG_RGMII1_RXC_SCT_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_RXC_OEX_EN   0x6c
#define  G1_PINMUX_REG_REG_RGMII1_RXC_OEX_EN_OFFSET 13
#define  G1_PINMUX_REG_REG_RGMII1_RXC_OEX_EN_MASK   0x2000
#define  G1_PINMUX_REG_REG_RGMII1_RXC_OEX_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_REFCLKO_PU_EN   0x70
#define  G1_PINMUX_REG_REG_RGMII1_REFCLKO_PU_EN_OFFSET 2
#define  G1_PINMUX_REG_REG_RGMII1_REFCLKO_PU_EN_MASK   0x4
#define  G1_PINMUX_REG_REG_RGMII1_REFCLKO_PU_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_REFCLKO_PD_EN   0x70
#define  G1_PINMUX_REG_REG_RGMII1_REFCLKO_PD_EN_OFFSET 3
#define  G1_PINMUX_REG_REG_RGMII1_REFCLKO_PD_EN_MASK   0x8
#define  G1_PINMUX_REG_REG_RGMII1_REFCLKO_PD_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_REFCLKO_PIN_SEL_EN   0x70
#define  G1_PINMUX_REG_REG_RGMII1_REFCLKO_PIN_SEL_EN_OFFSET 4
#define  G1_PINMUX_REG_REG_RGMII1_REFCLKO_PIN_SEL_EN_MASK   0xf0
#define  G1_PINMUX_REG_REG_RGMII1_REFCLKO_PIN_SEL_EN_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII1_REFCLKO_DRI_SEL   0x70
#define  G1_PINMUX_REG_REG_RGMII1_REFCLKO_DRI_SEL_OFFSET 8
#define  G1_PINMUX_REG_REG_RGMII1_REFCLKO_DRI_SEL_MASK   0xf00
#define  G1_PINMUX_REG_REG_RGMII1_REFCLKO_DRI_SEL_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII1_REFCLKO_SCT_EN   0x70
#define  G1_PINMUX_REG_REG_RGMII1_REFCLKO_SCT_EN_OFFSET 12
#define  G1_PINMUX_REG_REG_RGMII1_REFCLKO_SCT_EN_MASK   0x1000
#define  G1_PINMUX_REG_REG_RGMII1_REFCLKO_SCT_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_REFCLKO_OEX_EN   0x70
#define  G1_PINMUX_REG_REG_RGMII1_REFCLKO_OEX_EN_OFFSET 13
#define  G1_PINMUX_REG_REG_RGMII1_REFCLKO_OEX_EN_MASK   0x2000
#define  G1_PINMUX_REG_REG_RGMII1_REFCLKO_OEX_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_IRQ_PU_EN   0x74
#define  G1_PINMUX_REG_REG_RGMII1_IRQ_PU_EN_OFFSET 2
#define  G1_PINMUX_REG_REG_RGMII1_IRQ_PU_EN_MASK   0x4
#define  G1_PINMUX_REG_REG_RGMII1_IRQ_PU_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_IRQ_PD_EN   0x74
#define  G1_PINMUX_REG_REG_RGMII1_IRQ_PD_EN_OFFSET 3
#define  G1_PINMUX_REG_REG_RGMII1_IRQ_PD_EN_MASK   0x8
#define  G1_PINMUX_REG_REG_RGMII1_IRQ_PD_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_IRQ_PIN_SEL_EN   0x74
#define  G1_PINMUX_REG_REG_RGMII1_IRQ_PIN_SEL_EN_OFFSET 4
#define  G1_PINMUX_REG_REG_RGMII1_IRQ_PIN_SEL_EN_MASK   0xf0
#define  G1_PINMUX_REG_REG_RGMII1_IRQ_PIN_SEL_EN_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII1_IRQ_DRI_SEL   0x74
#define  G1_PINMUX_REG_REG_RGMII1_IRQ_DRI_SEL_OFFSET 8
#define  G1_PINMUX_REG_REG_RGMII1_IRQ_DRI_SEL_MASK   0xf00
#define  G1_PINMUX_REG_REG_RGMII1_IRQ_DRI_SEL_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII1_IRQ_SCT_EN   0x74
#define  G1_PINMUX_REG_REG_RGMII1_IRQ_SCT_EN_OFFSET 12
#define  G1_PINMUX_REG_REG_RGMII1_IRQ_SCT_EN_MASK   0x1000
#define  G1_PINMUX_REG_REG_RGMII1_IRQ_SCT_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_IRQ_OEX_EN   0x74
#define  G1_PINMUX_REG_REG_RGMII1_IRQ_OEX_EN_OFFSET 13
#define  G1_PINMUX_REG_REG_RGMII1_IRQ_OEX_EN_MASK   0x2000
#define  G1_PINMUX_REG_REG_RGMII1_IRQ_OEX_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_MDC_PU_EN   0x78
#define  G1_PINMUX_REG_REG_RGMII1_MDC_PU_EN_OFFSET 2
#define  G1_PINMUX_REG_REG_RGMII1_MDC_PU_EN_MASK   0x4
#define  G1_PINMUX_REG_REG_RGMII1_MDC_PU_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_MDC_PD_EN   0x78
#define  G1_PINMUX_REG_REG_RGMII1_MDC_PD_EN_OFFSET 3
#define  G1_PINMUX_REG_REG_RGMII1_MDC_PD_EN_MASK   0x8
#define  G1_PINMUX_REG_REG_RGMII1_MDC_PD_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_MDC_PIN_SEL_EN   0x78
#define  G1_PINMUX_REG_REG_RGMII1_MDC_PIN_SEL_EN_OFFSET 4
#define  G1_PINMUX_REG_REG_RGMII1_MDC_PIN_SEL_EN_MASK   0xf0
#define  G1_PINMUX_REG_REG_RGMII1_MDC_PIN_SEL_EN_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII1_MDC_DRI_SEL   0x78
#define  G1_PINMUX_REG_REG_RGMII1_MDC_DRI_SEL_OFFSET 8
#define  G1_PINMUX_REG_REG_RGMII1_MDC_DRI_SEL_MASK   0xf00
#define  G1_PINMUX_REG_REG_RGMII1_MDC_DRI_SEL_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII1_MDC_SCT_EN   0x78
#define  G1_PINMUX_REG_REG_RGMII1_MDC_SCT_EN_OFFSET 12
#define  G1_PINMUX_REG_REG_RGMII1_MDC_SCT_EN_MASK   0x1000
#define  G1_PINMUX_REG_REG_RGMII1_MDC_SCT_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_MDC_OEX_EN   0x78
#define  G1_PINMUX_REG_REG_RGMII1_MDC_OEX_EN_OFFSET 13
#define  G1_PINMUX_REG_REG_RGMII1_MDC_OEX_EN_MASK   0x2000
#define  G1_PINMUX_REG_REG_RGMII1_MDC_OEX_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_MDIO_PU_EN   0x7c
#define  G1_PINMUX_REG_REG_RGMII1_MDIO_PU_EN_OFFSET 2
#define  G1_PINMUX_REG_REG_RGMII1_MDIO_PU_EN_MASK   0x4
#define  G1_PINMUX_REG_REG_RGMII1_MDIO_PU_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_MDIO_PD_EN   0x7c
#define  G1_PINMUX_REG_REG_RGMII1_MDIO_PD_EN_OFFSET 3
#define  G1_PINMUX_REG_REG_RGMII1_MDIO_PD_EN_MASK   0x8
#define  G1_PINMUX_REG_REG_RGMII1_MDIO_PD_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_MDIO_PIN_SEL_EN   0x7c
#define  G1_PINMUX_REG_REG_RGMII1_MDIO_PIN_SEL_EN_OFFSET 4
#define  G1_PINMUX_REG_REG_RGMII1_MDIO_PIN_SEL_EN_MASK   0xf0
#define  G1_PINMUX_REG_REG_RGMII1_MDIO_PIN_SEL_EN_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII1_MDIO_DRI_SEL   0x7c
#define  G1_PINMUX_REG_REG_RGMII1_MDIO_DRI_SEL_OFFSET 8
#define  G1_PINMUX_REG_REG_RGMII1_MDIO_DRI_SEL_MASK   0xf00
#define  G1_PINMUX_REG_REG_RGMII1_MDIO_DRI_SEL_BITS   0x4
#define  G1_PINMUX_REG_REG_RGMII1_MDIO_SCT_EN   0x7c
#define  G1_PINMUX_REG_REG_RGMII1_MDIO_SCT_EN_OFFSET 12
#define  G1_PINMUX_REG_REG_RGMII1_MDIO_SCT_EN_MASK   0x1000
#define  G1_PINMUX_REG_REG_RGMII1_MDIO_SCT_EN_BITS   0x1
#define  G1_PINMUX_REG_REG_RGMII1_MDIO_OEX_EN   0x7c
#define  G1_PINMUX_REG_REG_RGMII1_MDIO_OEX_EN_OFFSET 13
#define  G1_PINMUX_REG_REG_RGMII1_MDIO_OEX_EN_MASK   0x2000
#define  G1_PINMUX_REG_REG_RGMII1_MDIO_OEX_EN_BITS   0x1
